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FEATURES Complete Monolithic Resolver-to-Digital Converter Incremental Encoder Emulation (1024-Line) Absolute Serial Data (12-Bit) Differential Inputs 12-Bit Resolution Industrial Temperature Range 20-Lead PLCC Low Power (50 mW) APPLICATIONS Industrial Motor Control Servo Motor Control Industrial Gauging Encoder Emulation Automotive Motion Sensing and Control Factory Automation Limit Switching
Low Cost, Complete 12-Bit Resolver-to-Digital Converter AD2S90
FUNCTIONAL BLOCK DIAGRAM
REF SIN SIN LO COS COS LO NMC A B NM CS ANGLE HIGH ACCURACY SIN COS MULTIPLIER DIGITAL ANGLE DECODE LOGIC UP-DOWN COUNTER SIN ( -
)
P.S.D. AND VEL FREQUENCY SHAPING CLKOUT HIGH DYNAMIC RANGE V.C.O.
ERROR AMPLIFIER U/D CLK
DIR
LATCH
SCLK DATA
SERIAL INTERFACE
GENERAL DESCRIPTION
The AD2S90 is a complete 12-bit resolution tracking resolverto-digital converter. No external components are required to operate the device. The converter accepts 2 V rms 10% input signals in the range 3 kHz-20 kHz on the SIN, COS and REF inputs. A Type II servo loop is employed to track the inputs and convert the input SIN and COS information into a digital representation of the input angle. The bandwidth of the converter is set internally at 1 kHz within the tolerances of the device. The guaranteed maximum tracking rate is 500 rps. Angular position output information is available in two forms, absolute serial binary and incremental A quad B. The absolute serial binary output is 12-bit (1 in 4096). The data output pin is high impedance when Chip Select CS is logic HI. This allows the connection of multiple converters onto a common bus. Absolute angular information in serial pure binary form is accessed by CS followed by the application of an external clock (SCLK) with a maximum rate of 2 MHz. The encoder emulation outputs A, B and NM continuously produce signals equivalent to a 1024 line encoder. When decoded this corresponds to 12 bits of resolution. Three common north marker pulsewidths are selected via a single pin (NMC). An analog velocity output signal provides a representation of velocity from a rotating resolver shaft traveling in either a clockwise or counterclockwise direction.
The AD2S90 operates on 5 V dc 5% power supplies and is fabricated on Analog Devices' Linear Compatible CMOS process (LC2MOS). LC2MOS is a mixed technology process that combines precision bipolar circuits with low power CMOS logic circuits.
PRODUCT HIGHLIGHTS
Complete Resolver-Digital Interface. The AD2S90 provides the complete solution for digitizing resolver signals (12-bit resolution) without the need for external components. Dual Format Position Data. Incremental encoder emulation in standard A QUAD B format with selectable North Marker width. Absolute serial 12-bit angular binary position data accessed via simple 3-wire interface. Single High Accuracy Grade in Low Cost Package. 10.6 arc minutes of angular accuracy available in a 20-lead PLCC. Low Power. Typically 50 mW power consumption.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
5%, AD2S90-SPECIFICATIONS (V = +5 Vnoted) V otherwise
DD
SS
= -5 V
5%, AGND = DGND = 0 V, TA = -40 C to +85 C unless
Units V rms kHz nA M mV peak dB V rms kHz nA k Degrees Hz rps MHz ms ms arc min LSB rps/V dc V dc A V dc V dc A pF Test Condition Sinusoidal Waveforms, Differential SIN to SINLO, COS to COSLO VIN = 2 10% V rms VIN = 2 10% V rms CMV @ SINLO, COSLO w.r.t. AGND @ 10 kHz Sinusoidal Waveform
Parameter SIGNAL INPUTS Voltage Amplitude Frequency Input Bias Current Input Impedance Common-Mode Volts1 CMRR REFERENCE INPUT Voltage Amplitude Frequency Input Bias Current Input Impedance Permissible Phase Shift CONVERTER DYNAMICS Bandwidth Maximum Tracking Rate Maximum VCO Rate (CLKOUT) Settling Time 1 Step 179 Step ACCURACY Angular Accuracy2 Repeatability3 VELOCITY OUTPUT Scaling Output Voltage at 500 rps Load Drive Capability LOGIC INPUTS SCLK, CS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance LOGIC OUTPUTS DATA, A, B,4 NM, CLKOUT, DIR Output High Voltage Output Low Voltage SERIAL CLOCK (SCLK) SCLK Input Rate NORTH MARKER CONTROL (NMC) 90 180 360 POWER SUPPLIES VDD VSS IDD ISS
Min 1.8 3 1.0
Typ 2.0
Max 2.2 20 100 100
60 1.8 3 100 -10 700 500 2.048 840 2.0 3.35 20 100 +10 1000
Relative to SIN, COS Inputs
2
7 20 10.6 + 1 LSB 1
120 2.78
150 3.33
180 4.17 250
VOUT = 2.5 V dc (typ), RL 10 k VDD = +5 V dc, VSS = -5 V dc VDD = +5 V dc, VSS = -5 V dc
3.5 1.5 10 10
4.0 1.0 0.4 2 +4.75 -0.75 -4.75 +4.75 -4.75 +5.0 DGND -5.0 +5.00 -5.00 +5.25 +0.75 -5.25 +5.25 -5.25 10 10
V dc V dc V dc MHz V dc V dc V dc V dc V dc mA mA
VDD = +5 V dc, VSS = -5 V dc IOH = 1 mA IOL = 1 mA IOL = 400 A
North Marker Width Relative to "A" Cycle
NOTES 1 If the tolerance on signal inputs = 5%, then CMV = 200 mV. 2 1 LSB = 5.3 arc minute. 3 Specified at constant temperature. 4 Output load drive capability. Specifications subject to change without notice.
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AD2S90 TIMING CHARACTERISTICS1, 2
CSB
(VDD = +5 V 5%, VSS = -5 V otherwise noted)
t2
5%, AGND = DGND = 0 V, TA = -40 C to +85 C unless
t6
t3
SCLK
t4
DATA MSB LSB
t*
t1
t5
t7
*THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 1. Serial Interface
NOTES 1 Timing data are not 100% production tested. Sample tested at +25C only to ensure conformance to data sheet limits. Logic output timing tests carried out using 10 pF, 100 k load. 2 Capacitance of data pin in high impedance state = 15 pF.
Parameter t1 t2 1 t3 t4 t5 t6 t7
AD2S90 150 600 250 250 100 600 150
Units ns max ns min ns min ns min ns max ns min ns max
Test Conditions/Notes CS to DATA Enable CS to 1st SCLK Negative Edge SCLK Low Pulse SCLK High Pulse SCLK Negative Edge to DATA Valid CS High Pulsewidth CS High to DATA High Z (Bus Relinquish)
NOTE 1 SCLK can only be applied after t2 has elapsed.
A
COUNTER IS CLOCKED ON THIS EDGE
B
CLKOUT
tCLK tABN
90
A, B, NM
NM
180
tDIR
DIR
360 NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
Figure 2. Incremental Encoder
Figure 3. DIR/CLKOUT/A, B and NM Timing
AD2S90 Parameter tDIR tCLK tABN Min 250 Max 200 400 250 Units ns ns ns Test Conditions/Notes DIR to CLKOUT Positive Edge CLKOUT Pulsewidth CLKOUT Negative Edge to A, B and NM Transition
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AD2S90
Power Supply Voltage (VDD - VSS) . . . . . . . . . . 5 V dc 5% Analog Input Voltage (SIN, COS & REF) . . . . . 2 V rms 10% Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10% Phase Shift between Signal and Reference . . . . . . . . . . . . . 10 Ambient Operating Temperature Range Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS PIN DESCRIPTIONS
Pin No. Mnemonic Function 1 2 AGND SIN Analog ground, reference ground. SIN channel noninverting input connect to resolver SIN HI output. SIN to SIN LO = 2 V rms 10%. SIN channel inverting input connect to resolver SIN LO. Serial interface data output. High impedance with CS = HI. Enabled by CS = 0. Serial interface clock. Data is clocked out on "first" negative edge of SCLK after a LO transition on CS. 12 SCLK pulses to clock data out. Chip select. Active LO. Logic LO transition enables DATA output. Encoder A output. Encoder B output. Encoder North Marker emulation output. Pulse triggered as code passes through zero. Three common pulsewidths available. Indicates direction of rotation of input. Logic HI = increasing angular rotation. Logic LO = decreasing angular rotation. Digital power ground return. Negative power supply, -5 V dc 5%. Positive power supply, +5 V dc 5%. Positive power supply, +5 V dc 5%. Must be connected to Pin 13. North marker width control. Internally pulled HI via 50 k nominal.
VDD to AGND . . . . . . . . . . . . . . . . . . . . -0.3 V dc to +7.0 V dc VSS to AGND . . . . . . . . . . . . . . . . . . . . +0.3 V dc to -7.0 V dc AGND to DGND . . . . . . . . . . . . -0.3 V dc to VDD + 0.3 V dc Analog Inputs to AGND REF . . . . . . . . . . . . . . . . . . VSS - 0.3 V dc to VDD + 0.3 V dc SIN, SIN LO . . . . . . . . . . . VSS - 0.3 V dc to VDD + 0.3 V dc COS, COS LO . . . . . . . . . . VSS - 0.3 V dc to VDD + 0.3 V dc Analog Output to AGND VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Digital Inputs to DGND, CSB, SCLK, RES . . . . . . . . . . . . . . . -0.3 V dc to VDD + 0.3 V dc Digital Outputs to DGND, NM, A, B, DIR, CLKOUT DATA . . . . . . -0.3 V dc to VDD + 0.3 V dc Operating Temperature Range Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300C Power Dissipation to +75C . . . . . . . . . . . . . . . . . . . . 300 mW Derates above +75C by . . . . . . . . . . . . . . . . . . . . . 10 mW/C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3 4 5
SIN LO DATA SCLK
6 7 8 9
CS A B NM
10
DIR
11 12 13 14
DGND VSS VDD VDD NMC
ORDERING GUIDE
Model Temperature Range Accuracy Package Option
15 16
AD2S90AP -40C to +85C
10.6 arc min P-20A
PIN CONFIGURATION
COS LO SIN LO AGND
CLKOUT Internal VCO clock output. Indicates angular velocity of input signals. Max nominal rate = 1.536 MHz. CLKOUT is a 300 ns positive pulse. VEL Indicates angular velocity of input signals. Positive voltage w.r.t. AGND indicates increasing angle. FSD = 375 rps. Converter reference input. Normally derived from resolver primary excitation. REF = 2 V rms nominal. Phase shift w.r.t. COS and SIN = 10 max COS channel inverting input. Connect to resolver COS LO. COS channel noninverting input. Connect to resolver COS HI output. COS = 2 V rms 10%.
17
3
2
1
COS
20
SIN
19
DATA 4 SCLK 5 CS 6 A7 B8
9 10 11
PIN 1 18 IDENTIFIER 17
REF VEL CLKOUT NMC VDD
18
REF
AD2S90
TOP VIEW (Not to Scale)
16 15 14
19 20
COS LO COS
12
13
CAUTION The AD2S90 features an input protection circuit consisting of large "distributed" diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charges Device Model). Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual.
DGND
VDD
VSS
NM
DIR
WARNING!
ESD SENSITIVE DEVICE
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AD2S90
RESOLVER FORMAT SIGNALS
A resolver is a rotating transformer which has two stator windings and one rotor winding. The stator windings are displaced mechanically by 90 (see Figure 4). The rotor is excited with an ac reference. The amplitude of subsequent coupling onto the stator windings is a function of the position of the rotor (shaft) relative to the stator. The resolver, therefore, produces two output voltages (S3-S1, S2-S4) modulated by the SINE and COSINE of shaft angle. Resolver format signals refer to the signals derived from the output of a resolver. Equation 1 illustrates the output form. S3-S1 = EO SIN t * SIN S2-S4 = EO SIN t * COS where: = shaft angle SIN t = rotor excitation frequency EO = rotor excitation amplitude (1)
For more information on the operation of the converter, see Circuit Dynamics section.
S2 TO S4 (COS)
S3 TO S1 (SIN)
R2 TO R4 (REF)
0
90
180
270
360
Principle of Operation
The AD2S90 operates on a Type 2 tracking closed-loop principle. The output continually tracks the position of the resolver without the need for external convert and wait states. As the transducer moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB. On the AD2S90, CLKOUT updates corresponding to one LSB increment. If we assume that the current word state of the up-down counter is , S3-S1 is multiplied by COS and S2-S4 is multiplied by SIN to give: EO SIN t * SIN COS EO SIN t * COS SIN An error amplifier subtracts these signals giving: EO SIN * (SIN COS - COS SIN ) or EO SIN t * SIN ( - ) where ( - ) = angular error A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null sin ( - ). When this is accomplished the word state of the up/down counter, , equals within the rated accuracy of the converter, the resolver shaft angle . (3) (2)
Figure 4. Electrical and Physical Resolver Representation
Refer to Figure 4. Positive power supply VDD = +5 V dc 5% should be connected to Pin 13 & Pin 14 and negative power supply VSS = -5 V dc 5% to Pin 12. Reversal of these power supplies will destroy the device. S3 (SIN) and S2 (COS) from the resolver should be connected to the SIN and COS pins of the converter. S1 (SIN) and S4 (COS) from the resolver should be connected to the SINLO and COSLO pins of the converter. The maximum signal level of either the SIN or COS resolver outputs should be 2 V rms 10%. The AD2S90 AGND pin is the point at which all analog signal grounds should be star connected. The SIN LO and COS LO pins on the AD2S90 should be connected to AGND. Separate screened twisted cable pairs are recommended for all analog inputs SIN, COS, and REF. The screens should terminate at the converter AGND pin. North marker width selection is controlled by Pin 15, NMC. Application of VDD, 0 V, or VSS to NMC will select standard 90, 180 and 360 pulsewidths. If unconnected, the NM pulse defaults to 90. For a more detailed description of the output formats available see the Position Output section.
Connecting The Converter
OSCILLATOR 10nF 10nF 47 F
+5V 0V (POWER GROUND) 47 F -5V VDD 13 VSS 12 DGND 11 10
18 REF TWISTED PAIR SCREENED CABLE S4 S2 19 20 1 2 3
17
16
15
14 VDD
COS LO COS AGND SIN SIN LO
AD2S90AP
5 6 7 8
9
S2 R1 R2
S4 S3 S1
4 S3 S1
RESOLVER POWER RETURN
Figure 5. Connecting the AD2S90 to a Resolver
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AD2S90
ABSOLUTE POSITION OUTPUT
SERIAL INTERFACE
Absolute angular position is represented by serial binary data and is extracted via a three-wire interface, DATA, CS and SCLK. The DATA output is held in a high impedance state when CS is HI. Upon the application of a Logic LO to the CS pin, the DATA output is enabled and the current angular information is transferred from the counters to the serial interface. Data is retrieved by applying an external clock to the SCLK pin. The maximum data rate of the SCLK is 2 MHz. To ensure secure data retrieval it is important to note that SCLK should not be applied until a minimum period of 600 ns after the application of a Logic LO to CS. Data is then clocked out, MSB first, on successive negative edges of the SCLK; 12 clock edges are required to extract the full 12 bits of data. Subsequent negative edges greater than the defined resolution of the converter will clock zeros from the data output if CS remains in a low state. If a resolution of less than 12 bits is required, the data access can be terminated by releasing CS after the required number of bits have been read.
t2
CSB
The north marker pulse is generated as the absolute angular position passes through zero. The AD2S90 supports the three industry standard widths controlled using the NMC pin. Figure 7 details the relationship between A, B and NM. The width of NM is defined relative to the A cycle.
INCREASING ANGLE
A
B
90
*NM
180
360 NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE LEVEL +VDD 0 -VSS WIDTH 90 180 360
t6
*SELECTABLE WITH THREE - LEVEL
CONTROL PIN "MARKER" DEFAULT TO 90 USING INTERNAL PULL - UP.
t3
SCLK
Figure 7. A, B and NM Timing
t4
DATA MSB LSB
t*
Unlike incremental encoders, the AD2S90 encoder output is not subject to error specifications such as cycle error, eccentricity, pulse and state width errors, count density and phase . The maximum speed rating, n, of an encoder is calculated from its maximum switching frequency, fMAX, and its ppr (pulses per revolution). n= 60 x f MAX PPR
t1
t5
t7
*THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 6. Serial Read Cycle
CS can be released a minimum of 100 ns after the last negative edge. If the user is reading data continuously, CS can be reapplied a minimum of 250 ns after it is released (see Figure 6). The maximum read time is given by: (12-bits read @ 2 MHz) Max RD Time = [600 + (12 x 500) + 600 + 100] = 7.30 s.
INCREMENTAL ENCODER OUTPUTS
The AD2S90 A, B pulses are initiated from CLKOUT which has a maximum frequency of 2.048 MHz. The equivalent encoder switching frequency is: 1/4 x 2.048 MHz = 512 kHz (4 updates = 1 pulse) At 12 bits the ppr = 1024, therefore the maximum speed, n, of the AD2S90 is: n= 60 x 512000 1024 This compares favorably with encoder specifications where fMAX is specified from 20 kHz (photo diodes) to 125 kHz (laser based) depending on the light system used. A 1024 line laser-based encoder will have a maximum speed of 7300 rpm. The inclusion of A, B outputs allows the AD2S90 + resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. = 30000 rpm
The incremental encoder emulation outputs A, B and NM are free running and are always valid, providing that valid resolver format input signals are applied to the converter. The AD2S90 emulates a 1024-line encoder. Relating this to converter resolution means one revolution produces 1024 A, B pulses. B leads A for increasing angular rotation (i.e., clockwise direction). The addition of the DIR output negates the need for external A and B direction decode logic. DIR is HI for increasing angular rotation.
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AD2S90
VELOCITY OUTPUT
The analog velocity output VEL is scaled to produce 150 rps/V dc 15%. The sense is positive V dc for increasing angular rotation. VEL can drive a maximum load combination of 10 k and 30 pF. The internal velocity scaling is fixed.
POSITION CONTROL
unless all parts of the system are backed up, a reset to a known datum point needs to take place. This can be extremely hazardous in many applications. The AD2S90 gets round this problem by supplying an absolute position serial data stream upon request, thus removing the need to reset to a known datum.
HOST I/O PORT TO HOST PROCESSOR COMMAND POSITION SEQUENCER (32-BIT) HOST INTERFACE POWER AMP DC MOTOR
The rotor movement of dc or ac motors used for servo control is monitored at all times. Feedback transducers used for this purpose detect either relative position in the case of an incremental encoder or absolute position and velocity using a resolver. An incremental encoder only measures change in position not actual position.
Closed Loop Control Systems
+ -
POSITION FEEDBACK PROCESSOR (32-BIT) DIGITAL PID DAC FILTER PORT (16-BIT) 8 - 12 DAC
The primary demand for a change in position must take into account the magnitude of that change and the associated acceleration and velocity characteristics of the servo system. This is necessary to avoid "hunting" due to over- or underdamping of the control employed. A position loop needs both actual and demand position information. Algorithms consisting of proportional, integral and derivative control (PID) may be implemented to control the velocity profile. A simplified position loop is shown in Figure 8.
POSITION CONTROLLER POSITION DEMAND SERVO AMP SERVO MOTOR
IN, A, B
INCREMENTAL POSITION
OPTIONAL VELOCITY FEEDBACK
AD2S90
ABSOLUTE POSITION RESOLVER
Figure 9. Practical Implementation of the AD2S90
DSP Interfacing
The AD2S90 serial output is ideally suited for interfacing to DSP configured microprocessors. Figures 10 to 13 illustrate how to configure the AD2S90 for serial interfacing to the DSP.
ADSP-2105 Interfacing
ACTUAL POSITION
AD2S90
RESOLVER
Figure 8. Position Loop
MOTION CONTROL PROCESSES
Advanced VLSI designs mean that silicon system blocks are now available to achieve high performance motion control in servo systems. A digital position control system using the AD2S90 is shown in Figure 9. In this system the task of determining the acceleration and velocity characteristics is fulfilled by programming a trapezoidal velocity profile via the I/O port. As can be seen from Figure 9 encoder position feedback information is used. This is a popular format and one which the AD2S90 emulates thereby facilitating the replacement of encoders with an AD2S90 and a resolver. However, major benefits can be realized by adopting the resolver principle as opposed to the incremental technique. Incremental feedback based systems normally carry out a periodic check between the position demanded by the controller and the increment position count. This requires software and hardware comparisons and battery backup in the case of power failure. If there is a supply failure and the drive system moves,
Figure 10 shows the AD2S90 interfaced to an ADSP-2105. The on-chip serial port of the ADSP-2105 is used in alternate framing receive mode with internal framing (internally inverted) and internal serial clock generation (externally inverted) options selected. In this mode the ADSP-2105 provides a CS and a serial clock to the AD2S90. The serial clock is inverted to prevent timing errors as a result of both the AD2S90 and ADSP2105 clock data on the negative edge of SCLK. The first data bit is void; 12 bits of significant data then follow on each consecutive negative edge of the clock. Data is clocked from the AD2S90 into the data receive register of the ADSP-2105. This is internally set to 13 bit (12 bits and one "dummy" bit) when 13 bits are received. The serial port automatically generates an internal processor interrupt. This allows the ADSP-2105 to read 12 significant bits at once and continue processing. The ADSP-2101, ADSP-2102, ADSP-2111 and 21msp50 can all interface to the AD2S90 with similar interface circuitry.
SCLK ADSP-2105 RFS DR
SCLK
AD2S90
CS DATA
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. ADSP-2105/AD2S90 Serial Interface
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AD2S90
TMS32020 Interfacing
Figure 11 shows the serial interface between the AD2S90 and the TMS32020. The interface is configured in alternate internal framing, external clock (externally inverted) mode. Sixteen bits of data are clocked from the AD2S90 into the data receive register (DRR) of the TMS32020. The DRR is fixed at 16 bits. To obtain the 12-significant bits, the processor needs to execute three right shifts. (First bit read is void, the last three will be zeros). When 16 bits have been received by the TMS32020, it generates an internal interrupt to read the data from the DRR.
Select the AD2S90 and frame the data. The S1 register is fixed at 16 bits, therefore, to obtain the 12-significant bits the processor needs to execute four right shifts. Once the NEC7720 has read 16 bits, an internal interrupt is generated to read the internal contents of the S1 register.
SCLK PD7720 SIEN S1
SCLK
AD2S90
CS DATA
SCLK TMS32020 FSR DRR
SCLK
AD2S90
CS DATA
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. PD7720/AD2S90 Serial Interface
EDGE TRIGGERED 4 DECODING LOGIC
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. TMS32020/AD2S90 Serial Interface
DSP56000 Interface
In most data acquisition or control systems the A, B incremental outputs must be decoded into absolute information, normally a parallel word, before they can be utilized effectively. To decode the A, B outputs on the AD2S90 the user must implement a 4x decoding architecture. The principle states that one A, B cycle represents 4 LSB weighted increments of the converter (see Equation 4). Up = (A) * B + (B) * A + (A) * B + () * A Down = (A) * B + (B) * A + (A) * B + (B) * A (4)
Figure 12 shows a serial interface between the AD2S90 and the DSP56000. The DSP in configured for normal mode synchronous operation with gated clock with SCLK and SC1 as outputs. SC1 is applied to CS.
SCLK DSP56000 SC1 SRD
SCLK
AD2S90
CS
CLOCKWISE ROTATION CH A
COUNTER CLOCKWISE ROTATION
DATA
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
CH B
Figure 12. DSP56000/AD2S90 Serial Interface
The DSP56000 assumes valid data on the first falling edge of SCLK. SCLK is inverted to ensure that the valid data is clocked in after one leading bit. The receive data shift register (SRD) is set for a 13-bit word. When this register has received 13 bits of data, it generates an internal interrupt on the DSP56000 to read the 12 bits of significant data from the register.
NEC7720 Interface
UP
DOWN
Figure 14. Principles of 4x Decoding
The algorithms in Equation 4 can be implemented using the architecture shown in Figure 15. Traditionally the direction of the shaft is decoded by determining whether A leads B. The AD2S90 removes the need to derive direction by supplying a direction output state which can be fed straight into the updown counter. For further information on this topic please refer to the application note "Circuit Applications of the AD2S90 Resolver-toDigital Converters."
Figure 13 shows the serial interface between the NEC7720 and the AD2S90. The NEC7720 expects data on the rising edge of its SCLK output, and therefore unlike the previous interfaces no inverter is required to clock data into the S1 register. There is no need to ignore the first data bit read. SIEN is used to Chip
CHA EDGE GENERATOR CHB A A B B
CLOCK U/D RESET UP/DOWN COUNTER PARALLEL DIGITAL OUTPUT
DIRECTION
Figure 15. 4x Decoding Incremental to Parallel Conversion
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AD2S90
REMOTE MULTIPLE SENSOR INTERFACING
The AD2S90 acceleration constant is given by:
The DATA output of the AD2S90 is held in a high impedance state until CS is taken LO. This allows a user to operate the AD2S90 in an application with more than one converter connected on the same line. Figure 16 shows four resolvers interfaced to four AD2S90s. Excitation for the resolvers is provided locally by an oscillator. SCLK, DATA and two address lines are fed down low loss cables suitable for communication links. The two address lines are decoded locally into CS for the individual converters. Data is received and transmitted using transmitters and receivers.
2-4 DECODING (74HC139) 4 RES1 4 RES2 4 RES3 4 RES4 2 2 BUFFER OSC AD2S90 1 AD2S90 2 AD2S90 3 AD2S90 4 CS1 CS2 CS3 CS4 A0 A1
K a = K1 x K 2 3.0 x 106 sec -2
(8)
The AD2S90's design has been optimized with a critically damped response. The closed-loop transfer function is given by:
OUT = IN 1+ st1 s2 s 3t2 1+ st1 + + K1K 2 K1K 2
(9)
The normalized gain and phase diagrams are given in Figures 18 and 19.
5 0 -5
SCLK
-10
DATA
-15 -20
VDD VSS 0V
-25 -30 -35
Figure 16. Remote Sensor Interfacing
CIRCUIT DYNAMICS/ERROR SOURCES Transfer Function
-40 -45 1 10 100 FREQUENCY - Hz 1k 10k
The AD2S90 operates as a Type 2 tracking servo loop. An integrator and VCO/counter perform the two integrations inherent in a Type 2 loop. The overall system response of the AD2S90 is that of a unity gain second order low-pass filter, with the angle of the resolver as the input and the digital position data as the output. Figure 17 illustrates the AD2S90 system diagram.
VEL OUT IN A1 (S) A2 (S) OUT
Figure 18. AD2S90 Gain Plot
0 -20 -40 -60 -80 -100 -120 -140
Figure 17. AD2S90 Transfer Function
The open-loop transfer function is given by:
K K (1 + st1 ) OUT = 12 2 1 + st2 IN s
-160 -180 1 10
(5)
100 FREQUENCY - Hz
1k
10k
Figure 19. AD2S90 Phase Plot
where:
A1(s) = K1 1+ st1 s 1+ st2
t1 = 1.0 ms t2 = 90 s
(6)
A2(s) =
K2 s
K1 = 4.875V /(LSB x sec) K 2 = 614, 400 LSB /(V x sec)
(7)
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AD2S90
The small step response is given in Figure 20, and is the time taken for the converter to settle to within 1 LSB. ts = 7.00 ms (maximum) The large step response (steps >20) applies when the error voltage will exceed the linear range of the converter. Typically it will take three times longer to reach the first peak for a 179 step. In response to a velocity step [VELOUT/(d/dt)] the velocity output will exhibit the same response characteristics as outlined above.
SOURCES OF ERROR
Acceleration Error A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant Ka of the converter.
Ka = Input Acceleration Error in Output Angle
(10)
The numerator and denominator's units must be consistent. Ka does not define maximum input acceleration, only the error due to its acceleration. The maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. Angular Error x Ka = degrees/sec2 (11) Ka can be used to predict the output position error for a given input acceleration. The AD2S90 has a fixed Ka = 3.0 x 106 sec-2 if we apply an input accelerating at 100 revs/sec2, the error can be calculated as follows:
Error in LSBs = Input Acceleration LSB / sec 2
a -2
10
DEGREES
0
[ K [sec ]
]
(12)
0
4
8
12
16
20
Figure 20. Small Step Response
=
100 rev / sec2 x 212 LSB / rev 3.0 x 10 sec
6
[
]
[
[
-2
]
] = 0.14 LSBs
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AD2S90
AD2S90/AD2S99 TYPICAL CONFIGURATION
Figure 21 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S90 Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S90 should be 2 V rms 10%. All the analog ground signals should be star connected to the AD2S90 AGND pin. If shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S90 AGND pin. The SYNREF output of the AD2S99 should be connected to the REF input pin of the AD2S90 via a 0.1 F capacitor with a 100 k resistor to GND. This is to block out any dc offset in the SYNREF signal. For more detailed information please refer to the AD2S99 data sheet.
VSS 4.7 F FBIAS SEL1 SEL2 VSS VSS 0.1 F
NC = NO CONNECT NC 4 SIN 5 DGND 6 COS 7 SEL2 = GND SEL1 = VSS FOUT = 5kHz NC 8
3
2
1
20 19 18 EXC EXC AGND
AD2S99
TOP VIEW (Not to Scale)
17 16
15 NC 14 NC
9
10 11 12 13 VDD LOS NC
NC SYNREF
50k
4.7 F
VDD 0.1 F
0.1 F 100k 18 17 16 15 14 REF VDD 13 COS LO COS AGND SIN SIN LO 4 R4 RESOLVER S1 5 VSS 12 DGND 11 VDD 4.7 F 4.7 F 0.1 F 0.1 F VSS
19 20 1 S2 R2 REF COS S4 S3 SIN 2 3
AD2S90
TOP VIEW (Not to Scale) 6 7 8
10 9
Figure 21. AD2S90 and AD2S99 Example Configuration
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AD2S90
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
P-20A 20-Lead Plastic Leaded Chip Carrier (PLCC)
C1653b-2-1/99
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
3 4 19 18 PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 8 9 14 13
0.050 (1.27) BSC
0.020 (0.50) R
0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78)
0.020 (0.50) R
PIN 1 IDENTIFIER
BOTTOM VIEW
(PINS UP)
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PRINTED IN U.S.A.

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